SH7750_08 Datasheet, PDF (115/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 1 Overview
Pin
No. Pin Name I/O
Function
Reset
Memory Interface
SRAM DRAM SDRAM PCMCIA MPX
194 TDO
O
Data out
(H-UDI)
195 VDD
Power Internal VDD
196 VSS
Power Internal GND
(0 V)
197 TMS
I
Mode (H-UDI)
198 TCK
I
Clock (H-UDI)
199 TDI
I
Data in (H-UDI)
200 TRST
I
Reset (H-UDI)
201 VDD-PLL2 Power PLL2 VDD (3.3V)
202 VSS-PLL2 Power PLL2 GND (0V)
203 VDD-PLL1 Power PLL1 VDD (3.3V)
204 VSS-PLL1 Power PLL1 GND (0V)
205 VDD-CPG Power CPG VDD (3.3V)
206 VSS-CPG Power CPG GND (0V)
207 XTAL
O
Crystal resonator
208 EXTAL
I
External input
clock/crystal
resonator
Legend:
I:
Input
O:
Output
I/O: Input/output
Power: Power supply
Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in
hardware standby mode.
Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the
on-chip PLL circuits are used.
Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-
chip crystal oscillation circuit is used.
Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-
chip RTC is used.
VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package.
The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP package.
For a QFP package, the maximum operating frequency of the external bus is 84 MHz.
* Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.
Rev.7.00 Oct. 10, 2008 Page 31 of 1074
REJ09B0366-0700