SH7750_08 Datasheet, PDF (49/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4.3.6 RAM Mode .......................................................................................................... 123
4.3.7 OC Index Mode.................................................................................................... 124
4.3.8 Coherency between Cache and External Memory ............................................... 125
4.3.9 Prefetch Operation ............................................................................................... 125
4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only)................................... 125
4.4 Instruction Cache (IC)....................................................................................................... 128
4.4.1 Configuration ....................................................................................................... 128
4.4.2 Read Operation .................................................................................................... 130
4.4.3 IC Index Mode ..................................................................................................... 131
4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S) .......................................... 131
4.5.1 IC Address Array ................................................................................................. 131
4.5.2 IC Data Array....................................................................................................... 132
4.5.3 OC Address Array................................................................................................ 133
4.5.4 OC Data Array ..................................................................................................... 135
4.6 Memory-Mapped Cache Configuration (SH7750R) ......................................................... 136
4.6.1 IC Address Array ................................................................................................. 137
4.6.2 IC Data Array....................................................................................................... 138
4.6.3 OC Address Array................................................................................................ 139
4.6.4 OC Data Array ..................................................................................................... 141
4.6.5 Summary of the Memory-Mapping of the OC..................................................... 142
4.7 Store Queues ..................................................................................................................... 142
4.7.1 SQ Configuration ................................................................................................. 142
4.7.2 SQ Writes............................................................................................................. 143
4.7.3 Transfer to External Memory............................................................................... 143
4.7.4 SQ Protection ....................................................................................................... 145
4.7.5 Reading the SQs (SH7750R Only) ...................................................................... 145
4.7.6 SQ Usage Notes ................................................................................................... 146
Section 5 Exceptions........................................................................................................... 149
5.1 Overview........................................................................................................................... 149
5.1.1 Features................................................................................................................ 149
5.1.2 Register Configuration......................................................................................... 149
5.2 Register Descriptions ........................................................................................................ 150
5.3 Exception Handling Functions .......................................................................................... 151
5.3.1 Exception Handling Flow .................................................................................... 151
5.3.2 Exception Handling Vector Addresses ................................................................ 151
5.4 Exception Types and Priorities ......................................................................................... 152
5.5 Exception Flow ................................................................................................................. 155
5.5.1 Exception Flow .................................................................................................... 155
5.5.2 Exception Source Acceptance.............................................................................. 156
Rev.7.00 Oct. 10, 2008 Page xlix of lxxxiv
REJ09B0366-0700