SH7750_08 Datasheet, PDF (260/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
(13) User Breakpoint Trap
• Source: Fulfilling of a break condition set in the user break controller
• Transition address: VBR + H'0000 0100, or DBR
• Transition operations:
In the case of a post-execution break, the PC contents for the instruction following the
instruction at which the breakpoint is set are set in SPC. In the case of a pre-execution break,
the PC contents for the instruction at which the breakpoint is set are set in SPC.
The SR and R15 contents when the break occurred are saved in SSR and SGR. Exception code
H'1E0 is set in EXPEVT.
The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. It is
also possible to branch to PC = DBR.
For details of PC, etc., when a data break is set, see section 20, User Break Controller (UBC).
User_break_exception()
{
SPC = (pre_execution break? PC : PC + 2);
SSR = SR;
SGR = R15;
EXPEVT = H'000001E0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = (BRCR.UBDE==1 ? DBR : VBR + H'00000100);
}
Rev.7.00 Oct. 10, 2008 Page 176 of 1074
REJ09B0366-0700