SH7750_08 Datasheet, PDF (27/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
16.1.3 Pin
Configuration
Table 16.1 SCIF Pins
Page
728
16.2.9 FIFO Control 747
Register (SCFCR2)
Bits 5 and 4—Transmit
FIFO Data Number
Trigger (TTRG1,
TTRG0):
Revision (See Manual for Details)
Note amended
Note: After a power-on reset, these pins function as mode input
pins MD1, MD2 and MD8. These pins can function as
serial pins by setting the SCIF operation with the TE, RE,
and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2.
These pins are made to function as serial pins by
performing SCIF operation settings with the TE, RE, and
CKE1 bits in SCSCR2 and the MCE bit in SCFCR2.
Break state transmission and detection can be set in the
SCIF's SCSPTR2 register.
Description amended
• SH7750
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
7 (9)
(Initial value)
1
3 (13)
1
0
1 (15)
1
0 (16)
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
16.2.11 Serial Port
Register (SCSPTR2)
• SH7750S/SH7750R
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
8 (8)
(Initial value)
1
4 (12)
1
0
2 (14)
1
1 (15)
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
750, 751 Description amended
Bit: 7
6
5
4
3
RTSIO RTSDT CTSIO CTSDT —
Initial value: 0
—
0
—
0
R/W: R/W R/W R/W R/W
R
2
1
0
— SPB2IO SPB2DT
—
0
—
R
R/W R/W
Bit 3—Reserved: This bit is always read as 0, and should only
be written with 0.
Bit 2—Reserved: The value of this bit is undefined when read.
The write value should always be 0.
17.1 Overview
775
Description amended
The serial communication interface (SCI) supports a subset of
the ISO/IEC 7816-3 (identification cards) standard as an
extended function.
17.1.3 Pin
777
Configuration
Table 17.1 Smart Card
Interface Pins
Note added
Note: The serial clock pin and transmit data pin function as
mode input pins MD0 and MD7 after a power-on reset
Rev.7.00 Oct. 10, 2008 Page xxvii of lxxxiv
REJ09B0366-0700