SH7750_08 Datasheet, PDF (445/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Name
Data enable 0
Data enable 1
Data enable 2
Data enable 3
Data enable 4
Signals
I/O
WE0/CAS0/ O
DQM0
WE1/CAS1/ O
DQM1
WE2/CAS2/ O
DQM2/ICIORD
WE3/CAS3/ O
DQM3/ICIOWR
WE4/CAS4/ O
DQM4
Section 13 Bus State Controller (BSC)
Description
When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: CAS signal for
D7–D0
When setting MPX interface: high-level output
In other cases: write strobe signal for D7–D0
When setting synchronous DRAM interface:
selection signal for D15–D8
When setting DRAM interface: CAS signal for
D15–D8
When setting PCMCIA interface: write strobe signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D15–D8
When setting synchronous DRAM interface:
selection signal for D23–D16
When setting DRAM interface: CAS signal for
D23–D16
When setting PCMCIA interface: ICIORD signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D23–D16
When setting synchronous DRAM interface:
selection signal for D31–D24
When setting DRAM interface: CAS signal for
D31–D24
When setting PCMCIA interface: ICIOWR signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D31–D24
When setting synchronous DRAM interface:
selection signal for D39–D32
When setting DRAM interface: CAS signal for
D39–D32
When setting MPX interface: high-level output
In other cases: write strobe signal for D39–D32
Rev.7.00 Oct. 10, 2008 Page 361 of 1074
REJ09B0366-0700