SH7750_08 Datasheet, PDF (319/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
19. LDC.L to SR: 4 issue cycles
I
D
EX
MA
S
D
SX
D
SX
D
SX
20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
I
D
SX
NA
S
D
SX
NA
S
21. STC.L from SGR: 3 issue cycles
I
D
SX
NA
S
D
SX
NA
S
D
SX
NA
S
22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
I
D
SX
NA
S
D
SX
MA
S
23. STC.L from SGR: 3 issue cycles
I
D
SX
NA
S
D
SX
NA
S
D
SX
MA
S
24. LDS to PR, JSR, BSRF: 2 issue cycles
I
D
EX
NA
S
D
SX
SX
25. LDS.L to PR: 2 issue cycles
I
D
EX
MA
S
D
SX
SX
26. STS from PR: 2 issue cycles
I
D
SX
NA
S
D
SX
NA
S
27. STS.L from PR: 2 issue cycles
I
D
SX
NA
S
D
SX
MA
S
28. CLRMAC, LDS to MACH/L: 1 issue cycle
I
D
EX
NA
S
F1
F1
F2
FS
29. LDS.L to MACH/L: 1 issue cycle
I
D
EX
MA
S
F1
F1
F2
FS
30. STS from MACH/L: 1 issue cycle
I
D
EX
NA
S
Figure 8.2 Instruction Execution Patterns (cont)
Rev.7.00 Oct. 10, 2008 Page 235 of 1074
REJ09B0366-0700