SH7750_08 Datasheet, PDF (571/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
In the case of a power-on reset, the bus state controller's registers are initialized, and therefore
the self-refresh state is cleared.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the
case of a manual reset.
CKIO
TRs1 TRs2 TRs3 TRs4
TRs5 Trc Trc Trc
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
BS
CKE
Figure 13.41 Synchronous DRAM Self-Refresh Timing
Rev.7.00 Oct. 10, 2008 Page 487 of 1074
REJ09B0366-0700