SH7750_08 Datasheet, PDF (953/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 User Break Controller (UBC)
instructions ahead of the branch instruction (when the branch is not made). In this case, the PC
value saved to SPC is the address of the branch destination (when the branch is made) or the
instruction following the delay slot instruction (when the branch is not made).
4. When operand access (address only) is set as a break condition, the address of the instruction
to be executed after the instruction at which the condition match occurred is saved to SPC.
The instruction at which the condition match occurred is executed, and a user break interrupt
occurs before the following instruction is executed.
5. When operand access (address + data) is set as a break condition, execution of the instruction
at which the condition match occurred is completed. A user break interrupt is generated before
execution of instructions from one instruction later to four instructions later. It is not possible
to specify at which instruction, from one later to four later, the interrupt will be generated. The
start address of the instruction after the instruction for which execution is completed at the
point at which user break interrupt handling is started is saved to SPC. If an instruction
between one instruction later and four instructions later causes another exception, control is
performed as follows. Designating the exception caused by the break as exception 1, and the
exception caused by an instruction between one instruction later and four instructions later as
exception 2, the fact that memory updating and register updating that essentially cannot be
performed by exception 2 cannot be performed is guaranteed irrespective of the existence of
exception 1. The program counter value saved is the address of the first instruction for which
execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump
destination and the value written to the exception register (EXPEVT/INTEVT) is not
guaranteed. However, if exception 2 is from a source not synchronized with an instruction
(external interrupt or peripheral module interrupt), exception 1 is used for the exception jump
destination and the value written to the exception register (EXPEVT/INTEVT).
20.3.8 Contiguous A and B Settings for Sequential Conditions
When channel A match and channel B match timings are close together, a sequential break may
not be guaranteed. Rules relating to the guaranteed range are given below.
1. Instruction access matches on both channel A and channel B
Instruction B is 0 instructions after
instruction A
Equivalent to setting the same address. Do not use
this setting.
Instruction B is 1 instruction after
instruction A
Sequential operation is not guaranteed.
Instruction B is 2 or more instructions Sequential operation is guaranteed.
after instruction A
Rev.7.00 Oct. 10, 2008 Page 869 of 1074
REJ09B0366-0700