SH7750_08 Datasheet, PDF (86/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 1 Overview
Item
CPU
Features
• Renesas Technology original SuperH architecture
• 32-bit internal data bus
• General register file:
⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers)
⎯ Seven 32-bit control registers
⎯ Four 32-bit system registers
• RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3)
⎯ Fixed 16-bit instruction length for improved code efficiency
⎯ Load-store architecture
⎯ Delayed branch instructions
⎯ Conditional execution
⎯ C-based instruction set
• Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
• Instruction execution time: Maximum 2 instructions/cycle
• Virtual address space: 4 Gbytes (448-Mbyte external memory space)
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• On-chip multiplier
• Five-stage pipeline
Rev.7.00 Oct. 10, 2008 Page 2 of 1074
REJ09B0366-0700