SH7750_08 Datasheet, PDF (443/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Note: * SH7750R only
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the BSC.
Section 13 Bus State Controller (BSC)
Bus
interface
RDY
CS6–CS0
CE2A–CE2B
BS
RD/FRAME
RD/WR
WE7–WE0
RAS
CAS7–CAS0, CASS
CKE
ICIORD, ICIOWR
REG
IOIS16
Interrupt
controller
Wait
control unit
Area
control unit
Memory
control unit
Refresh
control unit
WCR1
WCR2
WCR3
BCR1
BCR2
BCR3*
BCR4*
MCR
PCR
RFCR
RTCNT
Comparator
RTCOR
RTCSR
Legend:
WCR: Wait control register
BCR: Bus control register
MCR: Memory control register
PCR: PCMCIA control register
Note: * SH7750R only
RFCR: Refresh count register
RTCNT: Refresh timer count register
RTCOR: Refresh time constant register
RTCSR: Refresh timer control/status register
Figure 13.1 Block Diagram of BSC
BSC
Rev.7.00 Oct. 10, 2008 Page 359 of 1074
REJ09B0366-0700