|
SH7750_08 Datasheet, PDF (1146/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
|
◁ |
Appendix H Power-On and Power-Off Procedures
⯠When the LSI is mounted on a board and connected to other elements, ensure that â0.3 V <
Vin < VDDQ + 0.3 V. In addition, the time limit for the fall of power supply VDDQ and power
supply VDD from the minimum values in the LSIâs guaranteed operation voltage range (VDDQ
(min.) and VDD (min.)) to GND (0 V) is 150 ms (max.), as shown in figure H.2. The product
may be damaged if this time limit is exceeded. It is recommended that the power-off
sequence be completed in as short a time as possible.
H.3 Common Stipulations for Power-On and Power-Off
1. Always ensure that VDDQ = VDDâCPG = VDDâRTC = V . DDâPLL1/2
Refer to 9.8.5, Hardware Standby Mode Timing (SH7750S, SH7750R Only), regarding VDDâRTC
in hardware standby mode on the SH7750S and SH7750R.
2. Ensure that â0.3 V < VDD < VDDQ + 0.3 V.
3. Ensure that VSS = VSSQ = VSSâPLL1/2 = VSSâCPG = VSSâRTC = GND (0 V).
The product may be damaged if conditions 1., 2., and 3. above are not satisfied.
[V]
Power-on
Power supply
VDDQ
Power supply
VDD
Power-off
0.3 V (max)
0.3 V (max)
GND
[t]
Figure H.1 Power-On Procedure 1
Rev.7.00 Oct. 10, 2008 Page 1062 of 1074
REJ09B0366-0700
|
▷ |