SH7750_08 Datasheet, PDF (236/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
5.4 Exception Types and Priorities
Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.2 Exceptions
Exception Execution
Category Mode
Exception
Priority Priority Vector
Level Order Address
Exception
Offset Code
Reset
Abort type Power-on reset
1
1
H'A000 0000 —
H'000
Manual reset
1
2
H'A000 0000 —
H'020
H-UDI reset
1
1
H'A000 0000 —
H'000
Instruction TLB multiple-hit
1
3
H'A000 0000 —
H'140
exception
Data TLB multiple-hit exception 1
4
H'A000 0000 —
H'140
General Re-
User break before instruction 2
0
(VBR/DBR) H'100/— H'1E0
exception execution execution^*1
type
Instruction address error
2
1
(VBR)
H'100 H'0E0
Instruction TLB miss exception 2
2
(VBR)
H'400 H'040
Instruction TLB protection
2
3
(VBR)
violation exception
H'100 H'0A0
General illegal instruction
2
4
(VBR)
exception
H'100 H'180
Slot illegal instruction exception 2
4
(VBR)
H'100 H'1A0
General FPU disable exception 2
4
(VBR)
H'100 H'800
Slot FPU disable exception
2
4
(VBR)
H'100 H'820
Data address error (read)
2
5
(VBR)
H'100 H'0E0
Data address error (write)
2
5
(VBR)
H'100 H'100
Data TLB miss exception (read) 2
6
(VBR)
H'400 H'040
Data TLB miss exception (write) 2
6
(VBR)
H'400 H'060
Data TLB protection
2
7
(VBR)
violation exception (read)
H'100 H'0A0
Data TLB protection
2
7
(VBR)
violation exception (write)
H'100 H'0C0
FPU exception
2
8
(VBR)
H'100 H'120
Initial page write exception
2
9
(VBR)
H'100 H'080
Completion Unconditional trap (TRAPA) 2
type
User break after instruction
2
execution^*1
4
(VBR)
H'100 H'160
10
(VBR/DBR) H'100/— H'1E0
Rev.7.00 Oct. 10, 2008 Page 152 of 1074
REJ09B0366-0700