SH7750_08 Datasheet, PDF (622/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
BREQ
BACK
A25–A0
CSn
RD/WR
RD
WEn
D63–D0 (write)
BS
BREQ/BSACK
BACK/BSREQ
A25–A0
CSn
RD/WR
RD
WEn
D63–D0 (write)
BS
Hi-Z
Asserted for at least 2 cycles
Hi-Z
Negated within 2 cycles
Hi-Z
Hi-Z
Hi-Z
HiZ
Hi-Z
Hi-Z
Master mode device access
Must be asserted for
at least 2 cycles
Must be negated within 2 cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Slave mode device access
Master access
Slave access
Figure 13.79 Arbitration Sequence
Master access
Rev.7.00 Oct. 10, 2008 Page 538 of 1074
REJ09B0366-0700