SH7750_08 Datasheet, PDF (441/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Section 13 Bus State Controller (BSC)
13.1 Overview
The functions of the bus state controller (BSC) include division of the external memory space, and
output of control signals in accordance with various types of memory and bus interface
specifications. The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be
connected to this LSI, and also support the PCMCIA interface protocol, enabling system design to
be simplified and data transfers to be carried out at high speed by a compact system.
13.1.1 Features
The BSC has the following features:
• External memory space is managed as 7 independent areas
⎯ Maximum 64 Mbytes for each of areas 0 to 6
⎯ Bus width of each area can be set in a register (except area 0, which uses an external pin
setting)
⎯ Wait state insertion by RDY pin
⎯ Wait state insertion can be controlled by program
⎯ Specification of types of memory connectable to each area
⎯ Output the control signals of memory to each area
⎯ Automatic wait cycle insertion to prevent data bus collisions in case of consecutive
memory accesses to different areas, or a read access followed by a write access to the same
area
⎯ Write strobe setup time and hold time periods can be inserted in a write cycle to enable
connection to low-speed memory
• SRAM interface
⎯ Wait state insertion can be controlled by program
⎯ Wait state insertion by RDY pin
Connectable areas: 0 to 6
Settable bus widths: 64, 32, 16, 8
• DRAM interface
⎯ Row address/column address multiplexing according to DRAM capacity
⎯ Burst operation (fast page mode, EDO mode)
⎯ CAS-before-RAS refresh and self-refresh
Rev.7.00 Oct. 10, 2008 Page 357 of 1074
REJ09B0366-0700