SH7750_08 Datasheet, PDF (787/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Serial Communication Interface (SCI)
b. If the MPIE bit in the SCSCR1 register is cleared to 0
A multiprocessor interrupt indicating that data (ID) with the multiprocessor bit (MPB) set
to 1 was received, or a receive data full interrupt (RXI) occurred when data with the
multiprocessor bit (MPB) set to 0 and intended for this station was received.
2. Method for determining whether received data is ID or data
Do not use the MPB bit in the SCSSR1 register for software processing.
When using software processing to determine whether received data is ID (MPB = 1) or data
(MPB = 0), use a procedure such as saving a user-defined flag in memory to indicate receive
start.
Rev.7.00 Oct. 10, 2008 Page 703 of 1074
REJ09B0366-0700