SH7750_08 Datasheet, PDF (729/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the
settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
14.7.5 DMA Operation Register (DMAOR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDT DBL — — — — PR1 PR0 — — — — — AE NMIF DME
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R R R R R/W R/W R R R R R R/(W) R/(W) R/W
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For details
of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation Register
(DMAOR)
Bit 14⎯Number of DDT-Mode Channels (DBL): Selects the number of channels that are able
to accept external requests in DDT mode.
Bit 14: DBL
Description
0
Four DDT-mode channels
1
Eight DDT-mode channels
Note: When DMAOR.DBL = 0, channels 4 to 7 cannot accept external requests.
(Initial value)
When DMAOR.DBL = 1, one channel can be selected from among channels 0−7 by the
combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.14 shows the
channel selection by DTR format in the DDT mode.
Rev.7.00 Oct. 10, 2008 Page 645 of 1074
REJ09B0366-0700