SH7750_08 Datasheet, PDF (1077/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CKIO
A25–A0
CSn
RD/WR
RAS
CASn
D63–D0
(write)
TRr1
TRr2
TRr3
TRr4
t_AD
t_CSD
t_RWD
t_RASD
t_RASD
t_CASD1
t_CASD1
t_WDD
Section 22 Electrical Characteristics
TRr5
Trc
Trc
Trc
t_RASD
t_CASD1
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
t_DACD
t_DACD
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)
Rev.7.00 Oct. 10, 2008 Page 993 of 1074
REJ09B0366-0700