SH7750_08 Datasheet, PDF (209/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
4.3.8 Coherency between Cache and External Memory
Coherency between cache and external memory should be assured by software. In this LSI, the
following four new instructions are supported for cache operations. Details of these instructions
are given in the Programming Manual.
Invalidate instruction:
Purge instruction:
Write-back instruction:
Allocate instruction:
OCBI @Rn
OCBP @Rn
OCBWB @Rn
MOVCA.L R0,@Rn
Cache invalidation (no write-back)
Cache invalidation (with write-back)
Cache write-back
Cache allocation
4.3.9 Prefetch Operation
This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a
cache miss. If it is known that a cache miss will result from a read or write operation, it is possible
to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss
due to the read or write operation, and so improve software performance. If a prefetch instruction
is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or
a protection violation, the result is no operation, and an exception is not generated. Details of the
prefetch instruction are given in the Programming Manual.
Prefetch instruction:
PREF @Rn
4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only)
When cache enhanced mode (CCR.EMODE = 1) is specified and OC RAM mode (CCR.ORA =
1) is selected, in which half of the operand cache is used as internal RAM, internal RAM data may
be updated incorrectly.
Conditions Under which Problem Occurs: Incorrect data may be written to RAM when the
following four conditions are satisfied.
Condition 1: Cache enhanced mode (CCR.EMODE = 1) is specified.
Condition 2: The RAM mode (CCR.ORA = 1) in which half of the operand cache is used as
internal RAM is specified.
Condition 3: An exception or an interrupt occurs.
Rev.7.00 Oct. 10, 2008 Page 125 of 1074
REJ09B0366-0700