SH7750_08 Datasheet, PDF (536/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and
Tc2 the read data latch cycle.
CKIO
A25–A0
CSn
RD/WR
RAS
Tr1
Tr2
Tc1
Tc2
Tpc
Row
Column
CAS
D63–D0
(read)
D63–D0
(write)
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
The DACK is in the high-active setting
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.17 Basic DRAM Access Timing
Rev.7.00 Oct. 10, 2008 Page 452 of 1074
REJ09B0366-0700