SH7750_08 Datasheet, PDF (202/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
Effective address
31
26 25
13 12 10
54 2 0
OIX
ORA
22
RAM area
judgment
[13]
Entry
selection
Address array
9
(way 0, way 1)
3
0 Tag address U V
[12:5]
Longword (LW)
selection
Data array (way 0, way 1)
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
LRU
MMU
19
511 19 bits 1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit
Compare Compare
way 0 way 1
Read data
Write data
Hit signal
Figure 4.3 Configuration of Operand Cache (SH7750R)
Rev.7.00 Oct. 10, 2008 Page 118 of 1074
REJ09B0366-0700