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SH7750_08 Datasheet, PDF (645/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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Section 14 Direct Memory Access Controller (DMAC)
Bits 11 to 8âResource Select 3 to 0 (RS3âRS0): These bits specify the transfer request source.
Bit 11: Bit 10: Bit 9:
RS3 RS2 RS1
0
0
0
Bit 8:
RS0
0
Description
External request, dual address mode*1 *4 (external address
space â external address space)
(Initial value)
1
Setting prohibited
1
0
External request, single address mode
External address space â external device*1 *3 *4
1
External request, single address mode
External device â external address space*1 *3 *4
1
0
0
Auto-request (external address space â external address
space)*2
1
Auto-request (external address space â on-chip peripheral
module)*2
1
0
Auto-request (on-chip peripheral module â external address
space)*2
1
Setting prohibited
1
0
0
0
SCI transmit-data-empty interrupt transfer request
(external address space â SCTDR1)*2
1
SCI receive-data-full interrupt transfer request
(SCRDR1 â external address space)*2
1
0
SCIF transmit-data-empty interrupt transfer request
(external address space â SCFTDR2)*2
1
SCIF receive-data-full interrupt transfer request
(SCFRDR2 â external address space)*2
1
0
0
TMU channel 2 (input capture interrupt, external address space
â external address space)*2
1
TMU channel 2 (input capture interrupt, external address space
â on-chip peripheral module)*2
1
0
TMU channel 2 (input capture interrupt, on-chip peripheral
module â external address space)*2
1
Setting prohibited
Notes: 1. External request specifications are valid only for channels 0 and 1. Requests are not
accepted for channels 2 and 3 in normal DMA mode.
2. Dual address mode
3. In DDT mode, selection is possible with the DTR format [60] (R/W bit) and [57-56]
(MD1, MD0 bits) specification for channel 0 only.
4. In DDT mode:
Rev.7.00 Oct. 10, 2008 Page 561 of 1074
REJ09B0366-0700
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