SH7750_08 Datasheet, PDF (701/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
CMD
TDACK
ID1, ID0
Section 14 Direct Memory Access Controller (DMAC)
DTR
MD = 10 or 11
CA
D0 D1 D2 D3
WT
CA
D0 D1 D2 D3
WT
Start of data transfer
Next transfer request
Figure 14.34 Handshake Protocol without Use of Data Bus
(Channel 0 On-Demand Data Transfer)
Rev.7.00 Oct. 10, 2008 Page 617 of 1074
REJ09B0366-0700