SH7750_08 Datasheet, PDF (409/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Realtime Clock (RTC)
Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1
matches the respective counter values.
Bit 0: AF
Description
0
Alarm registers and counter values do not match
(Initial value)
[Clearing condition]
When 0 is written to AF
1
Alarm registers and counter values match*
[Setting condition]
When alarm registers in which the ENB bit is set to 1 and counter values
match*
Note: * Writing 1 does not change the value.
Bits 6, 5, 2, and 1—Reserved. The initial value of these bits is undefined. A write to these bits is
invalid, but the write value should always be 0.
11.2.16 RTC Control Register 2 (RCR2)
RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second
adjustment, and frequency divider RESET and RTC count control.
RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is
undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value
of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value.
Bit: 7
6
PEF PES2
Initial value: Undefined 0
R/W: R/W R/W
5
PES1
0
R/W
4
PES0
0
R/W
3
RTCEN
1
R/W
2
ADJ
0
R/W
1
0
RESET START
0
1
R/W R/W
Rev.7.00 Oct. 10, 2008 Page 325 of 1074
REJ09B0366-0700