SH7750_08 Datasheet, PDF (528/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
T1
Tw
T2
CKIO
A25–A0
CSn
RD/WR
RD
D63–D0
(read)
WEn
D63–D0
(write)
BS
RDY
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.11 SRAM Interface Wait Timing (Software Wait Only)
Rev.7.00 Oct. 10, 2008 Page 444 of 1074
REJ09B0366-0700