SH7750_08 Datasheet, PDF (830/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR2 can be read or written to by the CPU at all times.
SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 10 to 8 (SH7750)—Reserved: These bits are always read as 0, and should only be written
with 0.
Bits 10 to 8 (SH7750S, SH7750R)—RTS2 Output Active Trigger (RSTRG2, RSTG1, and
RSTG0): These bits output the high level to the RTS2 signal when the number of received data
stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the
table below.
Bit 10: RSTRG2 Bit 9: RSTRG1
0
0
1
1
0
1
Bit 8: RSTRG0
0
1
0
1
0
1
0
1
RTS2 Output Active Trigger
15
(Initial value)
1
4
6
8
10
12
14
Rev.7.00 Oct. 10, 2008 Page 746 of 1074
REJ09B0366-0700