SH7750_08 Datasheet, PDF (373/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10.2 Overview of CPG
Section 10 Clock Oscillation Circuits
10.2.1 Block Diagram of CPG
Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1
(2) a block diagram of the CPG in the SH7750R.
XTAL
EXTAL
MD8
Oscillator circuit
Crystal
oscillation
circuit
PLL circuit 1
×6
Frequency
divider 2
×1
×1/2
×1/3
×1/4
×1/6
×1/8
Frequency
divider 1
×1/2
CKIO
PLL circuit 2
×1
CPU clock (Ick)
cycle Icyc
Peripheral module
clock (Pck) cycle
Pcyc
Bus clock (Bck)
cycle Bcyc
MD2
MD1
MD0
CPG control unit
Clock frequency
control circuit
Standby control
circuit
FRQCR
STBCR
Bus interface
STBCR2
Legend:
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
Internal bus
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
Rev.7.00 Oct. 10, 2008 Page 289 of 1074
REJ09B0366-0700