SH7750_08 Datasheet, PDF (640/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
These registers are initialized to H'00000000 by a power-on or manual reset. They retain their
values in standby mode and deep sleep mode.
Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify
the space attribute for access to a PCMCIA interface area.
Bit 31: SSA2
0
1
Bit 30: SSA1
0
1
0
1
Bit 29: SSA0
0
1
0
1
0
1
0
1
Description
Reserved in PCMCIA access
Dynamic bus sizing I/O space
8-bit I/O space
16-bit I/O space
8-bit common memory space
16-bit common memory space
8-bit attribute memory space
16-bit attribute memory space
(Initial value)
Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait cycle
control for access to a PCMCIA interface area. This bit selects the wait control register in the BSC
that performs area 5 and 6 wait cycle control.
Bit 28: STC
Description
0
C5 space wait cycle selection
(Initial value)
Settings of bits A5W2–A5W0 in wait control register 2 (WCR2), and bits
A5PCW1–A5PCW0, A5TED2–A5TED0, and A5TEH2–A5TEH0 in the
PCMCIA control register (PCR), are selected
1
C6 space wait cycle selection
Settings of bits A6W2–A6W0 in wait control register 2 (WCR2), and bits
A6PCW1–A6PCW0, A6TED2–A6TED0, and A6TEH2–A6TEH0 in the
PCMCIA control register (PCR), are selected
Note: For details, see section 13.3.7, PCMCIA Interface.
Rev.7.00 Oct. 10, 2008 Page 556 of 1074
REJ09B0366-0700