SH7750_08 Datasheet, PDF (272/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Floating-Point Unit (FPU)
31 30
23 22
0
x
11111111
Nxxxxxxxxxxxxxxxxxxxxxx
N = 1: sNaN
N = 0: qNaN
Figure 6.3 Single-Precision NaN Bit Pattern
An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point
value.
• When the EN.V bit in the FPSCR register is 0, the operation result (output) is a qNaN.
• When the EN.V bit in the FPSCR register is 1, an invalid operation exception will be
generated. In this case, the contents of the operation destination register are unchanged.
If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been
input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit
in the FPSCR register. An exception will not be generated in this case.
The qNAN values generated by the FPU as operation results are as follows:
• Single-precision qNaN: H'7FBFFFFF
• Double-precision qNaN: H'7FF7FFFF FFFFFFFF
See the individual instruction descriptions for details of floating-point operations when a non-
number (NaN) is input.
6.2.3 Denormalized Numbers
For a denormalized number floating-point value, the exponent field is expressed as 0, and the
fraction field as a non-zero value.
When the DN bit in the FPU's status register FPSCR is 1, a denormalized number (source operand
or operation result) is always flushed to 0 in a floating-point operation that generates a value (an
operation other than copy, FNEG, or FABS).
When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is
processed as it is. See the individual instruction descriptions for details of floating-point
operations when a denormalized number is input.
Rev.7.00 Oct. 10, 2008 Page 188 of 1074
REJ09B0366-0700