SH7750_08 Datasheet, PDF (252/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
(5) Instruction TLB Protection Violation Exception
• Source: The access does not accord with the ITLB protection information (PR bits) shown
below.
PR
Privileged Mode
User Mode
0
Access possible
Access not possible
1
Access possible
Access possible
• Transition address: VBR + H'0000 0100
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR, and the contents of R15 are saved in SGR.
Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
ITLB_protection_violation_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'000000A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev.7.00 Oct. 10, 2008 Page 168 of 1074
REJ09B0366-0700