SH7750_08 Datasheet, PDF (39/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
22.3.3 Bus Timing 966
Figure 22.25
Synchronous DRAM
Normal Read Bus Cycle:
ACT + READ
Commands,
Burst (RASD = 1,
RCD[1:0] = 01, CAS
Latency = 3)
Figure 22.26
967
Synchronous DRAM
Normal Read Bus Cycle:
PRE + ACT + READ
Commands, Burst
(RASD = 1, RCD[1:0] =
01, TPC[2:0] = 001,
CAS Latency = 3)
Figure 22.27
968
Synchronous DRAM
Normal Read Bus Cycle:
READ Command, Burst
(RASD = 1, CAS
Latency = 3)
Figure 22.30
971
Synchronous DRAM
Normal Write Bus Cycle:
ACT + WRITE
Commands, Burst
(RASD = 1, RCD[1:0] =
01, TRWL[2:0] = 010)
Figure 22.31
972
Synchronous DRAM
Normal Write Bus Cycle:
PRE + ACT + WRITE
Commands, Burst
(RASD = 1, RCD[1:0] =
01, TPC[2:0] = 001,
TRWL[2:0] = 010)
Revision (See Manual for Details)
Title amended
Title amended
Title amended
Title amended
Title amended
Rev.7.00 Oct. 10, 2008 Page xxxix of lxxxiv
REJ09B0366-0700