SH7750_08 Datasheet, PDF (918/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Interrupt Controller (INTC)
Interrupt Source
INTEVT Interrupt Priority IPR (Bit
Code (Initial Value) Numbers)
Priority within
IPR Setting Unit
TMU3 TUNI3^*2
H'B00 15–0 (0)
INTPRI00
—
(11–8)
TMU4 TUNI4^*2
H'B80 15–0 (0)
INTPRI00
—
(15–12)
TMU0 TUNI0
H'400 15–0 (0)
IPRA (15–12) —
TMU1 TUNI1
H'420 15–0 (0)
IPRA (11–8) —
TMU2 TUNI2
H'440 15–0 (0)
IPRA (7–4) High
TICPI2
H'460
Low
RTC
ATI
PRI
CUI
H'480
H'4A0
H'4C0
15–0 (0)
IPRA (3–0)
High
↑⏐↓
Low
SCI
ERI
RXI
TXI
TEI
H'4E0
H'500
H'520
H'540
15–0 (0)
IPRB (7–4)
High
↑
⏐
⏐
↓
Low
SCIF ERI
RXI
BRI
TXI
H'700
H'720
H'740
H'760
15–0 (0)
IPRC (7–4)
High
↑
⏐
⏐
↓
Low
WDT ITI
H'560 15–0 (0)
IPRB (15–12) —
REF
RCMI
H'580 15–0 (0)
IPRB (11–8) High
ROVI
H'5A0
Low
Legend:
TUNI0–TUNI4: Underflow interrupts
TICPI2: Input capture interrupt
ATI: Alarm interrupt
PRI: Periodic interrupt
CUI: Carry-up interrupt
ERI: Receive-error interrupt
RXI: Receive-data-full interrupt
TXI: Transmit-data-empty interrupt
TEI: Transmit-end interrupt
BRI: Break interrupt request
ITI: Interval timer interrupt
Default
Priority
High
↑
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
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⏐
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⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
↓
Low
Rev.7.00 Oct. 10, 2008 Page 834 of 1074
REJ09B0366-0700