SH7750_08 Datasheet, PDF (342/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
8.4 Usage Notes
The following are additional notes on pipeline operation and the method of calculating the number
of clock cycles.
The number of states (I clock cycles) required for stages where an external bus access, etc., occurs
may include an increased number of cycles, in addition to the number of memory access cycles set
by the bus state controller (BSC), etc.
For example, the occurrence of the following may result in idle cycles as observed from the
external bus.
1. Transfer of data from the logical address bus to the physical address bus
2. Transfer of data between buses using different operation clocks
The stages where external memory access occurs include some instruction fetch (I) and some
memory access (MA) stages.
Rev.7.00 Oct. 10, 2008 Page 258 of 1074
REJ09B0366-0700