SH7750_08 Datasheet, PDF (496/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address
hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is set
to 1.
Bit 2: A6TEH2
0
1
Bit 1: A6TEH1
0
1
0
1
Bit 0: A6TEH0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Rev.7.00 Oct. 10, 2008 Page 412 of 1074
REJ09B0366-0700