SH7750_08 Datasheet, PDF (79/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Table 13.1 BSC Pins ................................................................................................................ 360
Table 13.2 BSC Registers ........................................................................................................ 364
Table 13.3 External Memory Space Map................................................................................. 366
Table 13.4 PCMCIA Interface Features ................................................................................... 368
Table 13.5 PCMCIA Support Interfaces .................................................................................. 369
Table 13.6 MPX Interface is Selected (Areas 0 to 6) ............................................................... 398
Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 423
Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 424
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment .......................... 425
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment .......................... 426
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ............................ 427
Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment ................. 428
Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment ................. 429
Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment ....................... 430
Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment ....................... 431
Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment ......................... 432
Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing... 451
Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address
Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) ........................... 468
Table 13.17 Cycles for which Pipeline Access is Possible......................................................... 484
Table 13.18 Relationship between Address and CE when Using PCMCIA Interface ............... 502
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1 DMAC Pins ............................................................................................................ 549
Table 14.2 DMAC Pins in DDT Mode .................................................................................... 550
Table 14.3 DMAC Registers .................................................................................................... 550
Table 14.4 Selecting External Request Mode with RS Bits ..................................................... 570
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits ...................... 572
Table 14.6 Supported DMA Transfers ..................................................................................... 576
Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode ......... 582
Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode ....... 583
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode ..................... 584
Table 14.10 Conditions for Transfer between External Memory and an External Device with
DACK, and Corresponding Register Settings ........................................................ 602
Table 14.11 DMAC Pins ............................................................................................................ 636
Table 14.12 DMAC Pins in DDT Mode .................................................................................... 637
Table 14.13 Register Configuration ........................................................................................... 638
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)....................................... 646
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode ............................ 648
Rev.7.00 Oct. 10, 2008 Page lxxix of lxxxiv
REJ09B0366-0700