SH7750_08 Datasheet, PDF (713/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Four requests can be queued
CLK
1st 2nd 3rd 4th
5th
DBREQ
BAVL
TR
Handshaking is necessary
to send additional requests
A25–A0
D63–D0
RAS,
CAS, WE
TDACK
ID1, ID0
RA
CA
CA
CA
CA
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
BA
WT
WT
WT
WT
Must be ignored
(no request transmitted)
Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer/Direct Data Transfer Request to Channel 2
Rev.7.00 Oct. 10, 2008 Page 629 of 1074
REJ09B0366-0700