SH7750_08 Datasheet, PDF (178/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 3 Memory Management Unit (MMU)
issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in
figure 3.12.
MMUCR
31
26 25 24 23
18 17 16 15
10 9 8 7
3210
LRUI
—
URB
—
URC
SV
—
TI — AT
Entry specification
SQMD
PTEH
31
VPN
10 9 8 7
—
0
ASID
PTEL
31 29 28
10 9 8 7 6 5 4 3 2 1 0
—
PPN
— V SZ PR SZ C D SHWT
PTEA
31
432 0
—
TC SA
Write
Entry 0
Entry 1
Entry 2
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
UTLB
Figure 3.12 Operation of LDTLB Instruction
3.5.4 Hardware ITLB Miss Handling
In an instruction access, the SH-4 searches the ITLB. If it cannot find the necessary address
translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and
if the necessary address translation information is present, it is recorded in the ITLB. This
Rev.7.00 Oct. 10, 2008 Page 94 of 1074
REJ09B0366-0700