SH7750_08 Datasheet, PDF (480/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
• When DRAM or Synchronous DRAM Interface is Set*¹
Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Notes: 1. External wait input is always ignored.
2. RAS down mode is prohibited.
Description
DRAM CAS
Assertion Width
Synchronous DRAM
CAS Latency Cycles
1
Inhibited
2
1^*2
3
2
4
3
7
4^*2
10
5^*2
13
Inhibited
16
Inhibited
Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states
to be inserted for area 1. For details on MPX interface setting, see table 13.6, MPX Interface is
Selected (Areas 0 to 6).
Bit 8: A1W2
0
1
Bit 7: A1W1
0
1
0
1
Bit 6: A1W0
0
1
0
1
0
1
0
1
Description
Inserted Wait States
RDY Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Rev.7.00 Oct. 10, 2008 Page 396 of 1074
REJ09B0366-0700