SH7750_08 Datasheet, PDF (161/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 3 Memory Management Unit (MMU)
URC: UTLB replace counter
SQMD: Store queue mode bit
SV: Single virtual mode bit
TI: TLB invalidate
AT: Address translation bit
Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00
0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR
rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an
instruction that performs data access to the P0, P3, U0, or store queue area should be located at
least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0,
P3, or U0 area should be located at least eight instructions after the MMUCR update instruction.
MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated
by hardware.
• LRUI: Least recently used ITLB. The LRU (least recently used) method is used to decide the
ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB
can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown
below. A dash in this table means that updating is not performed.
When ITLB entry 0 is used
When ITLB entry 1 is used
When ITLB entry 2 is used
When ITLB entry 3 is used
Other than the above
LRUI
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
—
—
—
1
—
—
0
0
—
—
1
—
1
—
0
—
—
1
—
1
1
—
—
—
—
—
—
When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by
an ITLB miss. An asterisk in this table means “don't care”.
Rev.7.00 Oct. 10, 2008 Page 77 of 1074
REJ09B0366-0700