SH7750_08 Datasheet, PDF (140/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 Programming Model
31
0 31
0 31
0
R0_BANK0^{*1 *2}
R1_BANK0^*2
R2_BANK0^*2
R3_BANK0^*2
R4_BANK0^*2
R5_BANK0^*2
R6_BANK0^*2
R7_BANK0^*2
R0_BANK1^{*1 *3}
R1_BANK1^*3
R2_BANK1^*3
R3_BANK1^*3
R4_BANK1^*3
R5_BANK1^*3
R6_BANK1^*3
R7_BANK1^*3
R0_BANK0^{*1 *4}
R1_BANK0^*4
R2_BANK0^*4
R3_BANK0^*4
R4_BANK0^*4
R5_BANK0^*4
R6_BANK0^*4
R7_BANK0^*4
R8
R8
R8
R9
R9
R9
R10
R10
R10
R11
R11
R11
R12
R12
R12
R13
R13
R13
R14
R14
R14
R15
R15
R15
SR
SR
SR
SSR
SSR
GBR
MACH
MACL
PR
GBR
MACH
MACL
PR
VBR
GBR
MACH
MACL
PR
VBR
PC
(a) Register configuration
in user mode
PC
SPC
SGR
DBR
R0_BANK0^{*1 *4}
R1_BANK0^*4
R2_BANK0^*4
R3_BANK0^*4
R4_BANK0^*4
R5_BANK0^*4
R6_BANK0^*4
R7_BANK0^*4
(b) Register configuration in
privileged mode (RB = 1)
PC
SPC
SGR
DBR
R0_BANK1^{*1 *3}
R1_BANK1^*3
R2_BANK1^*3
R3_BANK1^*3
R4_BANK1^*3
R5_BANK1^*3
R6_BANK1^*3
R7_BANK1^*3
(c) Register configuration in
privileged mode (RB = 0)
Notes: 1. The R0 register is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
2. Banked registers
3. Banked registers
Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
4. Banked registers
Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is set to 1.
Figure 2.2 CPU Register Configuration in Each Processor Mode
Rev.7.00 Oct. 10, 2008 Page 56 of 1074
REJ09B0366-0700