|
SH7750_08 Datasheet, PDF (727/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
|
◁ |
Section 14 Direct Memory Access Controller (DMAC)
Bit 19âDREQ Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the DREQ pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0âCHCR7. For details of the settings, see the description of the DS bit in section 14.2.4,
DMA Channel Control Registers 0â3 (CHCR0âCHCR3).
Bit 18âRequest Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of DREQ) is an active-high or active-low output.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control
Registers 0â3 (CHCR0âCHCR3).
Bit 17âAcknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0âCHCR7. (DDT mode: TDACK) For details of the settings, see the description of the AM
bit in section 14.2.4, DMA Channel Control Registers 0â3 (CHCR0âCHCR3).
Bit 16âAcknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control
Registers 0â3 (CHCR0âCHCR3).
Bits 15 and 14âDestination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode. For details of the settings, see the description of the DM1 and DM0 bits in section
14.2.4, DMA Channel Control Registers 0â3 (CHCR0âCHCR3).
Bits 13 and 12âSource Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4,
DMA Channel Control Registers 0â3 (CHCR0âCHCR3).
Rev.7.00 Oct. 10, 2008 Page 643 of 1074
REJ09B0366-0700
|
▷ |