SH7750_08 Datasheet, PDF (68/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait,
Bus Width: 32 Bits, Transfer Data Size: 64 Bits).................................................. 521
Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait
Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................... 522
Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait,
Bus Width: 32 Bits, Transfer Data Size: 64 Bits).................................................. 523
Figure 13.69 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait
Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................... 524
Figure 13.70 MPX Interface Timing 13 (Burst Read Cycle, AnW = 0, No External Wait,
Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)................................................ 525
Figure 13.71 MPX Interface Timing 14 (Burst Read Cycle, AnW = 0, External Wait Control,
Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 526
Figure 13.72 MPX Interface Timing 15 (Burst Write Cycle, AnW = 0, No External Wait,
Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 527
Figure 13.73 MPX Interface Timing 16 (Burst Write Cycle, AnW = 1, External Wait Control,
Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 528
Figure 13.74 Example of 64-Bit Data Width Byte Control SRAM............................................. 530
Figure 13.75 Byte Control SRAM Basic Read Cycle (No Wait) ................................................ 531
Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ....................... 532
Figure 13.77 Byte Control SRAM Basic Read Cycle
(One Internal Wait + One External Wait) .............................................................. 533
Figure 13.78 Waits between Access Cycles ................................................................................ 535
Figure 13.79 Arbitration Sequence.............................................................................................. 538
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.1 Block Diagram of DMAC ...................................................................................... 548
Figure 14.2 DMAC Transfer Flowchart .................................................................................... 568
Figure 14.3 Round Robin Mode ................................................................................................ 574
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode............................... 575
Figure 14.5 Data Flow in Single Address Mode ....................................................................... 577
Figure 14.6 DMA Transfer Timing in Single Address Mode.................................................... 578
Figure 14.7 Operation in Dual Address Mode........................................................................... 579
Figure 14.8 Example of Transfer Timing in Dual Address Mode ............................................. 580
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode ................................................... 581
Figure 14.10 Example of DMA Transfer in Burst Mode............................................................. 581
Figure 14.11 Bus Handling with Two DMAC Channels Operating............................................ 585
Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Level Detection), DACK (Read Cycle) ................................................................ 588
Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ
(Edge Detection), DACK (Read Cycle) ................................................................. 589
Rev.7.00 Oct. 10, 2008 Page lxviii of lxxxiv
REJ09B0366-0700