SH7750_08 Datasheet, PDF (1116/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix D CKIO2ENB Pin Configuration
CKIO2ENB
Description
0
RD2, RD/WR2, and CKIO2 have the same pin states as RD, RD/WR, and CKIO,
respectively
1
RD2, RD/WR2, and CKIO2 are in the high-impedance state
Note: CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases.
However, CKIO2 is not fed back.
Rev.7.00 Oct. 10, 2008 Page 1032 of 1074
REJ09B0366-0700