SH7750_08 Datasheet, PDF (463/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM
interface is used in area 6. When burst ROM interface is used, they also specify the number of
accesses in a burst. If area 6 is an MPX interface area, these bits are ignored.
Bit 7: A6BST2
0
Bit 6: A6BST1
0
Bit 5: A6BST0
0
1
1
0
1
1
0
0
1
1
0
1
Notes: Clear to 0 when PCMCIA interface is set.
* Settable only for SH7750R.
Description
Area 6 is accessed as SRAM interface
(Initial value)
Area 6 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, 32-, or 64*-bit
bus width
Area 6 is accessed as burst ROM
interface (8 consecutive accesses)
Can only be used with 8-, 16-, or 32-bit
bus width
Area 6 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
Area 6 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
Reserved
Reserved
Reserved
Rev.7.00 Oct. 10, 2008 Page 379 of 1074
REJ09B0366-0700