SH7750_08 Datasheet, PDF (310/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Instruction Set
Table 7.10 Floating-Point Double-Precision Instructions
Instruction
FABS
DRn
FADD
DRm,DRn
FCMP/EQ DRm,DRn
FCMP/GT DRm,DRn
FDIV
FCNVDS
FCNVSD
FLOAT
FMUL
FNEG
DRm,DRn
DRm,FPUL
FPUL,DRn
FPUL,DRn
DRm,DRn
DRn
FSQRT
FSUB
FTRC
DRn
DRm,DRn
DRm,FPUL
Operation
Instruction Code
Privileged T Bit
DRn & H'7FFF FFFF FFFF FFFF1111nnn001011101 —
—
→ DRn
DRn + DRm → DRn
1111nnn0mmm00000 —
—
When DRn = DRm, 1 → T
Otherwise, 0 → T
1111nnn0mmm00100 —
Comparison
result
When DRn > DRm, 1 → T
Otherwise, 0 → T
1111nnn0mmm00101 —
Comparison
result
DRn /DRm → DRn
1111nnn0mmm00011 —
—
double_to_ float[DRm] → FPUL 1111mmm010111101 —
—
float_to_ double [FPUL] → DRn 1111nnn010101101 —
—
(float)FPUL → DRn
1111nnn000101101 —
—
DRn * DRm → DRn
1111nnn0mmm00010 —
—
DRn ^ H'8000 0000 0000 0000 1111nnn001001101 —
—
→ DRn
DRn → DRn
DRn – DRm → DRn
1111nnn001101101 —
—
1111nnn0mmm00001 —
—
(long) DRm → FPUL
1111mmm000111101 —
—
Table 7.11 Floating-Point Control Instructions
Instruction
LDS Rm,FPSCR
LDS Rm,FPUL
LDS.L @Rm+,FPSCR
LDS.L @Rm+,FPUL
STS FPSCR,Rn
STS FPUL,Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Operation
Instruction Code
Privileged T Bit
Rm → FPSCR
0100mmmm01101010 —
—
Rm → FPUL
0100mmmm01011010 —
—
(Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 —
—
(Rm) → FPUL, Rm+4 → Rm 0100mmmm01010110 —
—
FPSCR → Rn
0000nnnn01101010 —
—
FPUL → Rn
0000nnnn01011010 —
—
Rn – 4 → Rn, FPSCR → (Rn) 0100nnnn01100010 —
—
Rn – 4 → Rn, FPUL → (Rn) 0100nnnn01010010 —
—
Rev.7.00 Oct. 10, 2008 Page 226 of 1074
REJ09B0366-0700