SH7750_08 Datasheet, PDF (565/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
BS
Section 13 Bus State Controller (BSC)
Tpr Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Trwl
Row
Row
H/L
Row
H/L
Row
c1
c1
c2
c3
c4
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.37 Burst Write Timing (Different Row Addresses)
Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between
an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the
DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally
divided into two or four banks, after a READ or WRIT command is issued for one bank it is
possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch
cycle, or during the data write cycle, and so shorten the access cycle.
Rev.7.00 Oct. 10, 2008 Page 481 of 1074
REJ09B0366-0700