SH7750_08 Datasheet, PDF (852/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.11 shows an example of the operation for reception in asynchronous mode.
Start
1 _bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
Serial
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
0/1
data
RDF
FER
One frame
RXI interrupt
request
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 16.11 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When
RTS2 is 0, reception is possible.
SH7750:
When RTS2 is 1, this indicates that SCFRDR2 contains 15 or more
bytes of data.
SH7750S, SH7750R: When RTS2 is 1, this indicates that SCFRDR2 contains a number of
data bytes equal to or greater than the RTS2 output active trigger set
number. The RTS2 output active trigger value is specified by bits 10 to
8 in the FIFO control register (SCFCR2), described in section 16.2.9,
FIFO control register (SCFCR2).
RTS2 also becomes 1 when bit 4 (RE) in SCSCR2 is 0.
Rev.7.00 Oct. 10, 2008 Page 768 of 1074
REJ09B0366-0700