SH7750_08 Datasheet, PDF (580/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
TRr1 TRr2 TRr3 TRr4 TRrw*¹ TRr1 TRr2 TRr3 TRr4 TRrw*² TRr5 Trc*² Trc*² Trc*² *³
CS3
RD/WR
RAS
CASS
DQMn
D63−D0
BS
CKE
MCR.TRAS[2:0]
MCR.TRAS[2:0] and MCR.TRC[2:0]
Notes: 1. The interval cycle number between the first and second REF commands is 4 + TRrw × m (m = 0 to 7)
CKIO cycles by the setting of the TRAS[2:0] bits.
2. The interval cycle number between the second REF command and the ACTV command after the refresh
operation is 4 + TRrw × m (m = 0 to 7) + 3Trc × n (n = 0 to 7) CKIO cycles by the setting of the TRAS[2:0]
bits and the TRC[2:0] bits.
3. The next ACTV command is issued at TRr3 to TRr5 (including TRrw × m) + 3Trc × n (n = 0 to 7) + 1
CKIO cycles after second REF command in this refresh operation. This 1 CKIO cycle is included in the
setting of the TRAS[2:0] bits. Set MCR.TRAS[2:0], MCR.TRC[2:0], RTCOR and RTCSR.CKS[2:0] so as
to satisfy the specification of the synchronous DRAM.
Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width
(TRAS[2:0] = 001, TRC[2:0] = 001)
Rev.7.00 Oct. 10, 2008 Page 496 of 1074
REJ09B0366-0700