SH7750_08 Datasheet, PDF (226/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
4.6.5 Summary of the Memory-Mapping of the OC
The address ranges to which the OC is memory-mapped in the double-sized cache mode of the
SH7750R are summarized below, using examples of data-array access.
• In normal mode (CCR.ORA = 0)
H'F500 0000 to H'F500 3FFF (16 KB ): Way 0 (entries 0 to 511)
H'F500 4000 to H'F500 7FFF (16 KB ): Way 1 (entries 0 to 511)
:
:
:
In the same pattern, shadows of the cache area are created in 32-Kbyte blocks until H'F5FF
FFFF.
• In RAM mode (CCR. ORA = 1)
H'F500 0000 to H'F500 1FFF (8 KB ): Way 0 (entries 0 to 255)
H'F500 2000 to H'F500 3FFF (8 KB ): Way 1 (entries 0 to 255)
:
:
:
In the same pattern, shadows of the cache area are created in 16-Kbyte blocks until H'F5FF
FFFF.
4.7 Store Queues
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory.
In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down
modes, in which SQ functions are stopped, can be used. The queue address control registers
(QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, Power-
Down Modes, for the procedure for stopping SQ functions.
4.7.1 SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store
queues can be set independently.
Rev.7.00 Oct. 10, 2008 Page 142 of 1074
REJ09B0366-0700