SH7750_08 Datasheet, PDF (579/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
cycles. The interval cycle number between the second REF command and the next ACTV
command issuance is specified by the settings of both the TRAS2–TRAS0 bits and the TRC2–
TRC0 bits in MCR in the sum total, which is 4 to 32 CKIO cycles. Set RTCOR and bits
CKS2–CKS0, and MCR so as to satisfy the refresh-interval rating of the synchronous DRAM
which you are using. The synchronous DRAM auto-refresh timing with 64-bit bus width is
shown below figure.
• When setting the mode register of the synchronous DRAM, set the address for area 2.
• Control signals required in this connection are RAS, CAS, RD/WR, CS3, DQM0−DQM7, and
CKE. CS2 is not used.
• Do not use partial-sharing mode. If you use this, correct operation is not guaranteed.
SH7750R
CKIO
CKE
CS3
RAS
CASS
RD/WR
A17
A16
A15–A3
D63–D48
DQM7
DQM6
D47–D32
DQM5
DQM4
D31–D16
DQM3
DQM2
D15–D0
DQM1
DQM0
CLK
CKE
CS
RAS
CAS
WE
BANK1
BANK0
A12–A0
I/O15–I/O0
DQMU
DQML
CLK
CKE
CS
RAS
CAS
WE
BANK1
BANK0
A12–A0
I/O15–I/O0
DQMU
DQML
CLK
CKE
CS
RAS
CAS
WE
BANK1
BANK0
A12–A0
I/O15–I/O0
DQMU
DQML
CLK
CKE
CS
RAS
CAS
WE
BANK1
BANK0
A12–A0
I/O15–I/O0
DQMU
DQML
Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width
(256 Mbits)
Rev.7.00 Oct. 10, 2008 Page 495 of 1074
REJ09B0366-0700