SH7750_08 Datasheet, PDF (784/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Serial Communication Interface (SCI)
Start of transmission
Read TEND flag in SCSSR1
TEND = 1?
No
Yes
Set MPBT bit in SCSSR1 to 1 and
write ID data to SCTDR1
Clear TDRE flag to 0
Read TEND flag in SCSSR1
TEND = 1?
No
Yes
Clear MPBT bit in SCSSR1 to 0
Write data to SCTDR1
Clear TDRE flag to 0
1. SCI status check and ID data write:
Read SCSSR1 and check that the
TEND flag is set to 1, then set the
MPBT bit in SCSSR1 to 1 and write
ID data to SCTDR1. Finally, clear the
TDRE flag to 0.
2. Preparation for data transfer: Read
SCSSR1 and check that the TEND
flag is set to 1, then set the MPBT bit
in SCSSR1 to 1.
3. Serial data transmission: Write the
first transmit data to SCTDR1, then
clear the TDRE flag to 0.
To continue data transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to SCTDR1, and then clear
the TDRE flag to 0. (Checking and
clearing of the TDRE flag is
automatic when the direct memory
access controller (DMAC) is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to SCTDR1.)
Read TDRE flag in SCSSR1
No
TDRE = 1?
Yes
No
All data transmitted?
Yes
End of transmission
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
Rev.7.00 Oct. 10, 2008 Page 700 of 1074
REJ09B0366-0700